Cryptographic hash functions have many security based applications in message authentication, digital signatures and data integrity. Secure Hash Algorithm-3(SHA-3) is a new cryptographic algorithm that was selected on Oct 2012 after five year public contest organized by National Institute of Standards and Technology (NIST), USA. This paper presents a compact and secured design of SHA-3 Algorithm on Xilinx Field Programmable Gate Array (FPGA) device Virtex-5. The design is logically optimized for area efficiency by merging Theta, Rho, and Pi steps of algorithm into single step. The security of the design is also increased by using a 64-bit LFSR. By logically merging these three steps, latency is reduced and maximum operating frequency of design is enhanced. Comparing the results with the previously reported FPGA implementations of SHA3-512, this design shows the best throughput per area (TPA) ratio of 47.
