Designing low power devices is now a major sector of research due to increased demand for portable devices. Because MOS devices are widespread, there is a great need for less energy consuming circuits, especially for portable devices and laptops. A memory element consumes 70 percent of total power in an integrated circuit. As flip-flops are the main area of memory elements used on any portable device, the major concern to reduce flip-flop energy consumption will help reduce power consumption in an IC considerably. In this paper we designed a flip-flop using CMOS logic; it consumes less energy than conventional gates designed. Transistors switching occurs when input and clock is applied. We proposed clocked D flip-flop, transient 0.7V power supply dissipation analysis and various applications of D flip-flop. This flip flop. This flip-flop is implemented using 45 nm Technology in virtuoso cadence.
