In this paper to implement a secure DPA resistant crypto secured processor such as advanced encryption standard (AES) and triple data encryption standard (DES), by secure side-channel attacks, such as differential power analysis (DPA). This methodology suitable for integration in a common automated standard cell ASIC or FPGA design flow. For stronger mitigation of DPA attacks, we proposed this design and analysis using high-performance adiabatic dynamic differential logic (PADDL) for mitigating DPA attacks for applications in secure integrated circuit (IC) design. A Penta MTJ-based gate that provides simple cascading, self-referencing, less voltage headroom downside in pre charge sense electronic equipment and low space. These types of gate will be implemented in (PADDL).For different logic gates and different writing circuitry is required but the sensing portion is remains identical. Therefore, the information is stored in the pinned layers using series or parallel combinations of transistors as per the logic storing in PentaMTJ. The logic gate is validated by simulation at the 22nm technology node using a tanner tool.
