Power dissipation and propagation delay are the major concern in modern CMOS VLSI designs. The reduction of threshold voltage increases the operational speed or computational speed of a digital logic circuit but it unfortunately increase in the sub-threshold leakage current as well and thereby it increases the static power dissipation of a circuit. Multi-threshold CMOS (MT-CMOS) technology provides a convenient solution for this problem, using which both sub-threshold leakage current and propagation delay of a digital logic can be reduced at a time simultaneously without any additional area overhead. Low[1]threshold voltage MOS transistors are used in the longest propagation path (critical path) to the reduce propagation delay. On the other hand, high threshold voltage MOS transistors are used in the shortest path to reduce the static power dissipation of a digital circuit. The paper describes the implementation and performance analysis of various low-power, high-speed digital logic design methodologies using 2μm technology of TANNER EDA back-end tools.
