The increasing demand for high density VLSI circuits the leakage current on the oxide thickness is becoming a key challenge in deep-sub-micron CMOS technology. The leakage power becomes a key for a low power design due to its increasing proportion in chip’s total power consumption in deep submicron technologies. Leakage power dissipation is playing a pivotal role in the total power decadence as threshold voltage becomes low as it is motivated by emerging battery-operated application on one hand and declining technology of deep sub micron on the other hand. Due to the difference between power, area and performance, various attempts have been done. This work is also based to minimize the power profligation of the VLSI circuits with the execution up to the acceptable level. Here we suggested Novel SRAM architecture called IP-SRAM with distinct write sub-cell and read sub-cell. In this paper we designed the total 8 bit SRAM architecture with newly suggested techniques and contrast this one with conventional SRAM architecture and we observed that the total power consumption is minimized. Here we used 180nm technology to design the total architecture. These results are contrasted this with deep submicron technologies.
