Adder plays a major role in any part of the combinational system like subtractions, high speed multiplication, DSPs and ALUs. Any computational system requires fast process to be carried out. Carry select adder (CSLA) is one of the high speed adder used in many computations to perform fast arithmetic operations. The logic operation involved in conventional carry select adder and binary to excess -1 converter based CSLA are analyzed to study the data dependence to identify redundant logic operations. The modified CSLA has been developed using gate-level modification to significantly reduce the delay and power of CSLA. Based on this modification 8-,16-,32-,64-,and 128-bit square root carry select adder(SQRT CSLA) architecture have been developed and compared with regular carry select adder architecture. The proposed design for higher adder has reduced power and delay is compared with the regular and modified SQRT CSLA. For 256-bit addition, it is proposed to simple gate level modification which significantly reduces the power by 19.4%. So this paper specially concentrates on speed and area constraints of CSLA.