Optimizing the interconnects plays an important role in core CPU architecture to obtain higher speeds. Interconnects consists of RC components, for which decreasing the RC delay plays an Important role. There are many Interconnect topologies but the optimal one helps in obtaining the minimal delay. The paper explains a new interconnect routing technique called Tapering to reduce this delay. Tapering routing topology helps in getting the minimal RC delay. It uses the Elmore delay model to get the minimal RC delay. The right percentage of tapering will fetch optimal results. Further implementation of this topology can be automated and can be effective in improvising the speed. In this technique, the resistance near the driver is made higher and the capacitance near the receiver is lowered. This leads to the improvement in RC delay. At first, the routing is done manually for a small portion of the chip and subsequently it is automated to do the routing for the entire section of the chip. Using the technique, it is observed that RC delay decreases by 10% to 30%
